struct_spi_master - interface to SPI master controller
2. SYNOPSIS ▲
structlist_head list; s16 bus_num; u16 num_chipselect; u16 dma_alignment; u16 mode_bits; u32 bits_per_word_mask; u16 flags;
#define SPI_MASTER_HALF_DUPLEX BIT(0)
#define SPI_MASTER_NO_RX BIT(1)
#define SPI_MASTER_NO_TX BIT(2)spinlock_t bus_lock_spinlock;
structmutex bus_lock_mutex; bool bus_lock_flag;
*spi); bool queued;
structkthread_work pump_messages; spinlock_t queue_lock;
*cur_msg; bool busy; bool running; bool rt;
3. MEMBERS ▲
device interface to this driver
link with the global spi_master list
board-specific (and often SOC-specific) identifier for a given SPI controller.
chipselects are used to distinguish individual SPI slaves, and are numbered from zero to num_chipselects. each slave has a chipselect signal, but itAqs common that not every chipselect is connected to a slave.
SPI controller constraint on DMA buffers alignment.
flags understood by this controller driver
A mask indicating which values of bits_per_word are supported by the driver. Bit n indicates that a bits_per_word n+1 is suported. If set, the SPI core will reject any transfer with an unsupported bits_per_word. If not set, this value is simply ignored, and itAqs up to the individual driver to perform any validation.
other constraints relevant to this driver
spinlock for SPI bus locking
mutex for SPI bus locking
indicates that the SPI bus is locked for exclusive use
updates the device mode and clocking records used by a deviceAqs SPI controller; protocol code may call this. This must fail if an unrecognized or unsupported mode is requested. ItAqs always safe to call this unless transfers are pending on the device whose settings are being modified.
adds a message to the controllerAqs transfer queue.
frees controller-specific state
whether this master is providing an internal message queue
thread struct for message pump
pointer to task for message pump kworker thread
work struct for scheduling work to the message pump
spinlock to syncronise access to message queue
the currently in-flight message
message pump is busy
message pump is running
whether this queue is set to run as a realtime task
a message will soon arrive from the queue so the subsystem requests the driver to prepare the transfer hardware by issuing this call
the subsystem calls the driver to transfer a single message while queuing transfers that arrive in the meantime. When the driver is finished with this message, it must call spi_finalize_current_message so the subsystem can issue the next transfer
there are currently no more messages on the queue so the subsystem notifies the driver that it may relax the hardware by issuing this call
Array of GPIOs to use as chip select lines; one per CS number. Any individual value may be -ENOENT for CS lines that are not GPIOs (driven by the SPI controller itself).
4. DESCRIPTION ▲
Each SPI master controller can communicate with one or more spi_device children. These make a small bus, sharing MOSI, MISO and SCK signals but not chip select signals. Each device may be configured to use a different clock rate, since those shared signals are ignored unless the chip is selected.
The driver for an SPI controller manages access to those devices through a queue of spi_message transactions, copying data between CPU memory and an SPI slave device. For each such message it queues, it calls the messageAqs completion function when the transaction completes.
5. COPYRIGHT ▲